경량화된 확산계층을 이용한 32-비트 구조의 소형 ARIA 연산기 구현
Vol. 16, No. 6, pp. 15-24,
12월.
2006
10.13089/JKIISC.2006.16.6.15, Full Text:
Keywords: ARIA processor, Diffusion, Light Weight, gate count
Abstract Statistics
Cite this article
10.13089/JKIISC.2006.16.6.15, Full Text:
Keywords: ARIA processor, Diffusion, Light Weight, gate count
Abstract Statistics
Cite this article
[IEEE Style]
G. Ryu, B. Koo, S. Yang, T. Chang, "Area Efficient Implementation of 32-bit Architecture of ARIA Block Cipher Using Light Weight Diffusion Layer," Journal of The Korea Institute of Information Security and Cryptology, vol. 16, no. 6, pp. 15-24, 2006. DOI: 10.13089/JKIISC.2006.16.6.15.
[ACM Style]
Gwon-Ho Ryu, Bon-Seok Koo, Sang-Woon Yang, and Tae-Joo Chang. 2006. Area Efficient Implementation of 32-bit Architecture of ARIA Block Cipher Using Light Weight Diffusion Layer. Journal of The Korea Institute of Information Security and Cryptology, 16, 6, (2006), 15-24. DOI: 10.13089/JKIISC.2006.16.6.15.