고속 RSA 하드웨어 곱셈 연산과 하드웨어 구조
Vol. 17, No. 1, pp. 11-20,
2월.
2007
10.13089/JKIISC.2007.17.1.11,
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Keywords: Montgomery multiplication, Redundant binary adder, Signed-digit system
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Keywords: Montgomery multiplication, Redundant binary adder, Signed-digit system
Abstract Statistics
Cite this article
[IEEE Style]
N. Chang, D. Lim, S. Ji, S. Yoon, C. Kim, "Fast RSA Montgomery Multiplier and Its Hardware Architecture," Journal of The Korea Institute of Information Security and Cryptology, vol. 17, no. 1, pp. 11-20, 2007. DOI: 10.13089/JKIISC.2007.17.1.11.
[ACM Style]
Nam-Su Chang, Dae-Sung Lim, Sung-Yeon Ji, Suk-Bong Yoon, and Chang-Han Kim. 2007. Fast RSA Montgomery Multiplier and Its Hardware Architecture. Journal of The Korea Institute of Information Security and Cryptology, 17, 1, (2007), 11-20. DOI: 10.13089/JKIISC.2007.17.1.11.